March 27, 2008
8:30 a.m. to 2:00 p.m. (Continental breakfast and lunch will be served)

The Clubhouse Restaurant [directions]
298 Oakbrook Center
Oak Brook, IL 60523-1841
(630) 472-0600
www.theclubhouse.com

Join us for a High-Frequency Seminar, part of Ansoft's technical application workshops for high-performance electronic design. In an effort to continue to provide support and stimulate industry response to current and future issues, we have put together a half-day seminar to present solutions that will be helpful in the Midwest design community.

We will explore the latest design techniques and simulation technologies in use by leading OEMs and suppliers in the areas of system signal integrity, RF and microwave systems, and EMI/EMC test and verification to achieve increased functionality, higher reliability, and more precise system-level performance in your designs.

This half day of technical presentations, networking, and discussion will put you on the path to first-pass system success!

We will have expert application engineers on hand to present and answer your questions. Presentation topics will include:

• Achieving Design Closure throughout IC/Package/Board Co-Design
• Understanding and Preventing EMI
• Design & Verification of an EPC Compliant Passive UHF RFID IC
• HFSS™/Ansoft Designer® Dynamic Link

For more information, contact Jonathan Fry at 219-477-4046 or jfry@ansoft.com.

Achieving Design Closure throughout IC/Package/Board Co-Design
Achieving design closure throughout IC/package/board is a critical requirement for system success in leading-edge, high-performance designs. This presentation highlights the strengthening of methodology through Ansoft technology to achieve first-pass system success. Real industry examples in Signal Integrity (SI), Power Integrity (PI), and Electromagnetic Interference (EMI) are shown, including simulation correlation to measurements. In the first example, a package signal integrity benchmark problem proposed in the 2006 Electrical Performance of Electronic Packaging special session is solved using Ansoft's solution. Different techniques from commercial vendors and academia using clusters of high-powered workstations to large supercomputer partitions were proposed and/or used to solve the problem over the course of several hours to days. Here, we used a single workstation using SIwave™ and achieved excellent correlation to the measurements provided using an extraction from DC to 30GHz in under two hours. For a Power Distribution Network (PDN) Analysis, a chip/package/board example using SIwave and an Apache Die power distribution model is shown followed by a Very Fine-pitch Ball Grid Array (VfBGA) Simultaneous Switching Output (SSO) Analysis and correlation. The presentation concludes with an EMI/EMC example where design changes are quantified in SIwave and then correlated to EMI test results.

Understanding and Preventing EMI
EMI continues to be a challenging problem for high-speed electronic designers; however, understanding and preventing EMI problems no longer requires a build-and-test approach. This presentation introduces some fundamental concepts regarding EMI, illustrates the root causes for EMI problems, and presents a systematic simulation procedure that can be followed to detect and reduce EMI problems early in the design cycle. First, different simulations used to prevent EMI from occurring to begin with will be discussed. Next, working together with engineers at EMC Corporation, the author investigates parallel plate resonances and via transitions and their effect on EMI. Case studies that compare simulation results to measurements will be shown and discussed. It will be demonstrated that the location and frequency of plane resonances with respect to via transitions has a direct effect on the magnitude of EMI and how engineers can employ simulation early in the design phase to avoid these problems. The author will show how proper signal and power integrity approaches can greatly reduce EMI issues downstream. In addition, the author will illustrate methods of simulating the behavior of PCB designs and their enclosures accurately and efficiently. The presentation will conclude with a demonstration of how to model and simulate the EMI effects in an entire system with enclosure.

Design & Verification of an EPC Compliant Passive UHF RFID IC
Radio Frequency Identification (RFID) is an electronic tagging technology that allows an object, place, or person to be automatically identified at a distance without a direct line-of-sight using a radio wave exchange. This presentation describes the design process and testing results for a Class 2 (Gen 2) UHF RFID system reference design. Details on the design and optimization of the rectifier (charge pump), the voltage regulator, the demodulator, and the modulator are highlighted. A system-level software verification of the RFID system, including co-simulation between the tag circuit and the reader/tag antennas, is also presented. The presentation concludes with a discussion on the measurement data.

HFSS/Ansoft Designer Dynamic Link
Ansoft has created a unique, two-way dynamic link between HFSS™ and Ansoft Designer®, Ansoft's circuit simulation environment. This link allows dimensions and material properties to be passed to HFSS by the circuit simulator; HFSS then returns multi-mode S-parameters back. By using HFSS and Ansoft Designer together via the dynamic link, designers can address more complex designs with reduced solve time. This presentation will demonstrate the power of this approach with RF, microwave, and high-speed channel examples.