Beyond 1 GHz, S-parameters provide the best representation of the electrical characteristics of very high-speed interconnects. HFSS™ provides GHz-accurate S-parameter and Full-Wave SPICE™ models for complex trace routing, vias and transitions, connectors and IC packages. High-performance electronic designs often include operating specifications for signal integrity in the time domain and for power integrity in the frequency domain. Common time-domain parameters, such as eye-diagrams, jitter, TDR measurements and SSN as well as frequency-domain metrics such as resonances, phase-noise margins, power plane impedance, and insertion loss appear within the same spec sheet. HFSS™ provides all of these swept frequency simulations with full-wave S-parameters generated by detailed electromagnetic analysis or combines with Nexxim® to provide accurate transient results. For high-speed differential transmission lines, HFSS produces differential S-parameters, allowing high-speed design engineers to achieve optimum signal path performance, determining route layer trade-offs, via stub and anti-pad radius impact.
Engineers designing servers, storage devices, multimedia PCs, entertainment systems, and telecom systems have driven an industry trend to replace legacy shared parallel buses with high-speed point-to-point serial buses. Standard interfaces like XAUI, XFI, Serial ATA, PCI Express, HDMI, and FB-DIMM have emerged to provide greater throughput using serial signaling rates of 2.5 to 10 Gb/s.
Trends toward point-to-point serial interconnects provide numerous and distinct system implementation advantages. In comparison with traditional parallel interfaces, serial solutions provide lower cost by using fewer I/O pins and simplified routing. Printed circuit board (PCB) area utilized for the interconnect can be reduced by more than 50% due to the utilization of fewer traces, fewer components, and elimination of on board termination elements. Differential signaling provides immunity to common mode noise, provides better voltage margins compared to single-ended solutions, and reduces electromagnetic interference (EMI) radiation. The serial nature of the interconnect eliminates the issues of data skew among multiple parallel lines. Finally, the clock is embedded in the serial data stream eliminating issues of timing and clock skew.
While these advantages compel the standardization and rapid adoption of serial links, it also has attendant challenges for system and board designers. Reliable signal transmission across a host board or between daughter cards on a backplane at GHz speeds compels adoption of new strategies and tools. This reference flow document (download above) outlines a reference design flow/methods to reliably characterize and design complex serial channels so that engineers can overcome the design challenges for high-speed serial interconnects. To illustrate this reference flow, specific circuits and interconnect examples are PCI Express-specific circuit and interconnect models and channel designs are used.
