

3D/2D Parasitic Extraction for High-Performance Electronic Design
IC packaging
IC packaging Related News »
Accurately characterize the performance of bond wires, signal paths, ground planes or pin/solder-ball terminations of an IC package.
With dramatic increases in pin counts, combined with ever-smaller IC package footprints, the signal path plays a critical role in determining the dielectric performance of the device. Using the integrated parametric and optimization capability with Q3D Extractor, designers can easily perform "what if" analysis to ensure that the signal path allows them to quickly and confidently deliver working solutions.
Q3D Extractor® is a critical tool used throughout the package-design community. It accurately characterizes the performance of the package, whether focusing on the bond wire, signal path, ground planes or pin/solder-ball terminations. This enables the designer to predict the system performance (silicon through the package) well before test, assembly and manufacture.
What's more, Q3D Extractor easily integrates into existing EDA design flows using AnsoftLinks™ to import layout information from Cadence, Synopsys, Mentor and Zuken directly into Q3D Extractor, where parasitic information is extracted and an equivalent circuit is generated. This equivalent circuit model can be used in Ansoft Designer® or other commercially available SPICE packages, where system and timing analysis can be performed.
On-chip | IC packaging | PCB structures
|