ANSYS TPA Features
ANSYS TPA delivers advanced technology for automated parasitic extraction for IC packages.
Advanced Quasi-static Solver
TPA contains advanced quasistatic 3-D electromagnetic field solvers based on the method of moments (MoM) accelerated by fast multipole method (FMM). The results provided by these solvers include proximity and skin effect, dielectric and ohmic loss, and frequency dependencies. The Q3D tool easily and quickly provides 3-D extraction of resistance (R), partial inductance (L), capacitance (C) and conductance (G).
Automated RLC Extraction Solver
TPA fully characterizes an entire package structure and automatically produces lumped or distributed RLC (resistance, inductance, and capacitance) values for any lead or coupled groups of leads in matrix format or in SPICE sub-circuit format. These models can be generated directly from package layout tools coming from Synopsys®, Cadence® and Zuken™, and exported into existing SPICE tools (SPICE/IBIS format) for subsequent timing analyses.
Intuitive Layout Editor Solver
TPA includes an intuitive 2-D layout-based interface that allows engineers to create and modify their package layouts and designs. TPA also has the ability to render geometry in 3-D with the integrated 3-D viewer.
The new 2-D layout editor and 3-D viewer allow:
- Creation of advanced wirebond or flip-chip designs from scratch or modify/correct designs imported from third-party layout tools
- System-in-package (SiP) designs with multiple wire-bond configurations including trace-to-trace, die-to-die, and cascaded
- User-defined wirebond profiles expanding shapes from JEDEC 4- and 5-point to include arbitrary polylines
- Complex solder ball models capture true shape and subsequent electrical performance of solder balls and flip-chip solder bumps
- Layer stack-up editing
- Via pad stack editing
- VB scripting support
- Performance of validation checks to verify setup including detection of self-intersecting polygons, disjoint nets, and overlapping (DC-shorted) nets, vias and bondwires as well as illegal connections between bonding pads and bondwires
Equivalent Circuit Creation Solver
TPA can be used to create equivalent circuit models (SPICE sub-circuits/ladder-type lumped models).
- Export for HSpice®, PSpice®, Spectre® RF, and other Berkeley-compatible SPICE tools
- Cadence® DML, Synopsys® SPEF, and IBIS .pkg model
Design Flow Integration Solver
TPA can be integrated directly into electronic package layout tools, such as Synopsys Encore™, Cadence® Advanced Package Designer (APD), and Zuken™ CR-5000, to provide package engineers with a seamless design flow, automatically generating RLC models. The resulting electrical models can then be exported to and analyzed within Ansoft Designer/ DesignerSI, ANSYS Nexxim or other SPICE-compatible circuit tools.
High-Performance Computing Solver
TPA can leverage available computing power for fast turnaround of detailed parasitic extraction, even on large design layouts. HPC enables the ability to distribute, by solution type, CG, AC RL, and DC RL solver engines over processors, cores and machines.
